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Publications of ches 2002
Page
Title
1
CHES: Past, Present, and Future
2-12
Optical Fault Induction Attacks
13-28
Template Attacks
29-45
The EM Side-Channel(s)
46-56
Enhanced Montgomery Multiplication
57-70
New Algorithm for Classical Modular Inverse
71-81
Increasing the Bitlength of a Crypto-Coprocessor
82-97
Enhancing Simple Power-Analysis Attacks on Elliptic Curve Cryptosystems
98-113
Implementation of Elliptic Curve Cryptography with Built-In Counter Measures against Side Channel Attacks
114-128
Secure Elliptic Curve Implementations: An Analysis of Resistance to Power-Attacks in a DSP Processor
129-143
Address-Bit Differential Power Analysis of Cryptographic Schemes OK-ECDH and OK-ECDSA
144-158
2Gbit/s Hardware Realizations of RIJNDAEL and SERPENT: A Comparative Analysis
159-171
Efficient Software Implementation of AES on 32-Bit Platforms
172-186
An Optimized S-Box Circuit Architecture for Low Power AES Design
187-197
Simplified Adaptive Multiplicative Masking for AES
198-212
Multiplicative Masking and Power Analysis of AES
213-227
Keeping Secrets in Hardware: The Microsoft Xbox? Case Study
228-243
A DPA Attack against the Modular Reduction within a CRT Implementation of RSA
244-259
Further Results and Considerations on Side Channel Attacks on RSA
260-275
Fault Attacks on RSA with CRT: Concrete Results and Practical Countermeasures
276-290
Some Security Aspects of the M IST Randomized Exponentiation Algorithm
291-302
The Montgomery Powering Ladder
303-317
DPA Countermeasures by Improving the Window Method
318-332
Efficient Subgroup Exponentiation in Quadratic and Sixth Degree Extensions
333-348
On the Efficient Generation of Elliptic Curves over Prime Fields
349-365
An End-to-End Systems Approach to Elliptic Curve Cryptography
366-380
A Low-Power Design for an Elliptic Curve Digital Signature Chip
381-399
A Reconfigurable System on Chip Implementation for Elliptic Curve Cryptography over GF(2
^{n}
)
400-414
Genus Two Hyperelliptic Curve Coprocessor
415-430
True Random Number Generator Embedded in Reconfigurable Hardware
431-449
Evaluation Criteria for True (Physical) Random Number Generators Used in Cryptographic Applications
450-453
A Hardware Random Number Generator
454-469
RFID Systems and Security and Privacy Implications
470-483
A New Class of Invertible Mappings
484-499
Scalable and Unified Hardware to Compute Montgomery Inverse in GF(p) and GF(2)
500-514
Dual-Field Arithmetic Unit for GF(p) and GF(2
^{m}
)
515-528
Error Detection in Polynomial Basis Multipliers over Binary Extension Fields
529-539
Hardware Implementation of Finite Fields of Characteristic Three
540-550
Preventing Differential Analysis in GLV Elliptic Curve Scalar Multiplication
551-563
Randomized Signed-Scalar Multiplication of ECC to Resist Power Attacks
564-578
Fast Multi-scalar Multiplication Methods on Elliptic Curves with Precomputation Strategy Using Montgomery Trick
579-592
Experience Using a Low-Cost FPGA Design to Crack DES Keys
593-609
A Time-Memory Tradeoff Using Distinguished Points: New Analysis & FPGA Results