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DPA Leakage Models for CMOS Logic Circuits

Authors:
Daisuke Suzuki
Minoru Saeki
Tetsuya Ichikawa
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DOI: 10.1007/11545262_27
URL: https://iacr.org/archive/ches2005/027.pdf
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Conference: CHES 2005
BibTeX
@inproceedings{ches-2005-786,
  title={DPA Leakage Models for CMOS Logic Circuits},
  booktitle={Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings},
  series={Lecture Notes in Computer Science},
  publisher={Springer},
  volume={3659},
  pages={366-382},
  url={https://iacr.org/archive/ches2005/027.pdf},
  doi={10.1007/11545262_27},
  author={Daisuke Suzuki and Minoru Saeki and Tetsuya Ichikawa},
  year=2005
}