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Paper: CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method

Authors:
Tetsuya Izu
Jun Kogure
Takeshi Shimoyama
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DOI: 10.1007/978-3-540-74735-2_25
URL: https://iacr.org/archive/ches2007/47270364/47270364.pdf
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Conference: CHES 2007
BibTeX
@inproceedings{ches-2007-821,
  title={CAIRN 2: An FPGA Implementation of the Sieving Step in the Number Field Sieve Method},
  booktitle={Cryptographic Hardware and Embedded Systems - CHES 2007, 9th International Workshop, Vienna, Austria, September 10-13, 2007, Proceedings},
  series={Lecture Notes in Computer Science},
  publisher={Springer},
  volume={4727},
  pages={364-377},
  url={https://iacr.org/archive/ches2007/47270364/47270364.pdf},
  doi={10.1007/978-3-540-74735-2_25},
  author={Tetsuya Izu and Jun Kogure and Takeshi Shimoyama},
  year=2007
}