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Paper: Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm

Authors:
Henry Kuo
Ingrid Verbauwhede
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DOI: 10.1007/3-540-44709-1_6
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Conference: CHES 2001
BibTeX
@inproceedings{ches-2001-697,
  title={Architectural Optimization for a 1.82Gbits/sec VLSI Implementation of the AES Rijndael Algorithm},
  booktitle={Cryptographic Hardware and Embedded Systems - CHES 2001, Third International Workshop, Paris, France, May 14-16, 2001, Proceedings},
  series={Lecture Notes in Computer Science},
  publisher={Springer},
  volume={2162},
  pages={51-64},
  doi={10.1007/3-540-44709-1_6},
  author={Henry Kuo and Ingrid Verbauwhede},
  year=2001
}