International Association for Cryptologic Research

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A5/3 make or break: A massively parallel FPGA architecture for exhaustive key search

Authors:
Konstantina Miteloudi
Lejla Batina
Nele Mentens
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DOI: 10.46586/tches.v2025.i3.361-388
URL: https://tches.iacr.org/index.php/TCHES/article/view/12220
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Abstract: In this paper, we have designed and implemented a massively parallel FPGA architecture for exhaustive key search on the A5/3 encryption algorithm. A5/3 is based on KASUMI, it has an effective key of 64 bits, and it is used in GSM (2G) mobile telephony systems. Despite the widespread adoption of more advanced technologies (4G, 5G), 2G networks remain as fallback options. In our novel hardware architecture, we use an AMD-Xilinx Alveo U250 card, with its FPGA configured to operate with 104 cores clocked at 496.7 M Hz, that can evaluate 235.59 keys/sec. Our results show that the $1 million attack can be achieved with 128 Alveo U250 cards, on average, in 16 days.
BibTeX
@article{tches-2025-35782,
  title={A5/3 make or break: A massively parallel FPGA architecture for exhaustive key search},
  journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
  publisher={Ruhr-Universität Bochum},
  volume={2025},
  pages={361-388},
  url={https://tches.iacr.org/index.php/TCHES/article/view/12220},
  doi={10.46586/tches.v2025.i3.361-388},
  author={Konstantina Miteloudi and Lejla Batina and Nele Mentens},
  year=2025
}