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SoC Root Canal! Root Cause Analysis of Power Side-Channel Leakage in System-on-Chip Designs

Authors:
Pantea Kiaei , Worcester Polytechnic Institute, Worcester, MA 01609, USA
Patrick Schaumont , Worcester Polytechnic Institute, Worcester, MA 01609, USA
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DOI: 10.46586/tches.v2022.i4.751-773
URL: https://tches.iacr.org/index.php/TCHES/article/view/9839
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Abstract: Finding the root cause of power-based side-channel leakage becomes harder when multiple layers of design abstraction are involved. While side-channel leakage originates in processor hardware, the dangerous consequences may only become apparent in the cryptographic software that runs on the processor. This contribution presents RootCanal, a methodology to explain the origin of side-channel leakage in a software program in terms of the underlying micro-architecture and system architecture. We simulate the hardware power consumption at the gate level and perform a non-specific test to identify the logic gates that contribute most sidechannel leakage. Then, we back-annotate those findings to the related activities in the software. The resulting analysis can automatically point out non-trivial causes of side-channel leakages. To illustrate RootCanal’s capabilities, we discuss a collection of case studies.
BibTeX
@article{tches-2022-32384,
  title={SoC Root Canal! Root Cause Analysis of Power Side-Channel Leakage in System-on-Chip Designs},
  journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
  publisher={Ruhr-Universität Bochum},
  volume={2022, Issue 4},
  pages={751-773},
  url={https://tches.iacr.org/index.php/TCHES/article/view/9839},
  doi={10.46586/tches.v2022.i4.751-773},
  author={Pantea Kiaei and Patrick Schaumont},
  year=2022
}