International Association for Cryptologic Research

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Paper: An energy and area efficient, all digital entropy source compatible with modern standards based on jitter pipelining

Authors:
Adriaan Peetermans , imec-COSIC, KU Leuven, Leuven, Belgium
Ingrid Verbauwhede , imec-COSIC, KU Leuven, Leuven, Belgium
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DOI: 10.46586/tches.v2022.i4.88-109
URL: https://tches.iacr.org/index.php/TCHES/article/view/9814
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Abstract: This paper proposes an energy and area efficient entropy source, suitable for true random number generation, accompanied with a stochastic model in a 28nm CMOS technology. The design uses a jitter pipelining architecture together with an increased timing resolution to achieve a maximal throughput of 298 Mbit/s and a best energy efficiency of 1.46 pJ/bit at a supply of 0.8V. The generated random bits pass the NIST SP 800-90B IID tests with a min entropy rate of 0.933 bit/bit, which is more than required by the AIS-31 standard. The all digital design allows for effortless transfer to other technology nodes, taking advantage of all benefits related to further technology scaling.
BibTeX
@article{tches-2022-32357,
  title={An energy and area efficient, all digital entropy source compatible with modern standards based on jitter pipelining},
  journal={IACR Transactions on Cryptographic Hardware and Embedded Systems},
  publisher={Ruhr-Universit├Ąt Bochum},
  volume={2022, Issue 4},
  pages={88-109},
  url={https://tches.iacr.org/index.php/TCHES/article/view/9814},
  doi={10.46586/tches.v2022.i4.88-109},
  author={Adriaan Peetermans and Ingrid Verbauwhede},
  year=2022
}