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Paper: FPGA and ASIC Implementations of the $\eta_T$ Pairing in Characteristic Three

Authors:
Jean-Luc Beuchat
Hiroshi Doi
Kaoru Fujita
Atsuo Inomata
Akira Kanaoka
Masayoshi Katouno
Masahiro Mambo
Eiji Okamoto
Takeshi Okamoto
Takaaki Shiga
Masaaki Shirase
Ryuji Soga
Tsuyoshi Takagi
Ananda Vithanage
Hiroyasu Yamamoto
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URL: http://eprint.iacr.org/2008/280
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Abstract: Since their introduction in constructive cryptographic applications, pairings over (hyper)elliptic curves are at the heart of an ever increasing number of protocols. As they rely critically on efficient algorithms and implementations of pairing primitives, the study of hardware accelerators became an active research area. In this paper, we propose two coprocessors for the reduced $\eta_T$ pairing introduced by Barreto {\it et al.} as an alternative means of computing the Tate pairing on supersingular elliptic curves. We prototyped our architectures on FPGAs. According to our place-and-route results, our coprocessors compare favorably with other solutions described in the open literature. We also present the first ASIC implementation of the reduced $\eta_T$ pairing.
BibTeX
@misc{eprint-2008-17957,
  title={FPGA and ASIC Implementations of the $\eta_T$ Pairing in Characteristic Three},
  booktitle={IACR Eprint archive},
  keywords={implementation / Tate pairing, $\eta_T$ pairing, elliptic curve cryptography, finite field, arithmetic, hardware accelerator, FPGA, ASIC},
  url={http://eprint.iacr.org/2008/280},
  note={ beuchat@risk.tsukuba.ac.jp 14053 received 20 Jun 2008, last revised 22 Jun 2008},
  author={Jean-Luc Beuchat and Hiroshi Doi and Kaoru Fujita and Atsuo Inomata and Akira Kanaoka and Masayoshi Katouno and Masahiro Mambo and Eiji Okamoto and Takeshi Okamoto and Takaaki Shiga and Masaaki Shirase and Ryuji Soga and Tsuyoshi Takagi and Ananda Vithanage and Hiroyasu Yamamoto},
  year=2008
}