International Association for Cryptologic Research

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Paper: Synthesis of Secure FPGA Implementations

Authors:
Kris Tiri
Ingrid Verbauwhede
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URL: http://eprint.iacr.org/2004/068
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Abstract: This paper describes the synthesis of Dynamic Differential Logic to increase the resistance of FPGA implementations against Differential Power Analysis. The synthesis procedure is developed and a detailed description is given of how EDA tools should be used appropriately to implement a secure digital design flow. Compared with an existing technique to implement Dynamic Differential Logic on FPGA, the technique saves a factor 2 in slice utilization. Experimental results also indicate that a secure version of the AES encryption algorithm can now be implemented with a mere 50% increase in time delay and 90% increase in slice utilization when compared with a normal non-secure single ended implementation.
BibTeX
@misc{eprint-2004-12042,
  title={Synthesis of Secure FPGA Implementations},
  booktitle={IACR Eprint archive},
  keywords={implementation / differential power analysis, FPGA, synthese},
  url={http://eprint.iacr.org/2004/068},
  note={ tiri@ee.ucla.edu 12476 received 28 Feb 2004},
  author={Kris Tiri and Ingrid Verbauwhede},
  year=2004
}