|Thursday, August 17th|
|7:00 am - 8:45 am
||Registration at Atwater Kent Building, WPI|
|Shuttle Service will be provided
between WPI, the Crowne Plaza and the Courtyard Marriott |
|8:45 am - 9:15 am
|| Welcome by Jack Carney (Provost, WPI)|
|Introductory remarks by Cetin Koc and Christof Paar|
| ||Session||Authors||Talk's Title|
|9:15 am - 9:55 am
||Alfred Menezes, University of Waterloo, Canada
||Elliptic curve cryptography in constrained environments.|
|9:55 am - 10:55 am
||Implementation of Elliptic Curve Cryptosystems
||S. Okada, N. Torii, K. Ito, and M. Takenaka.
||Implementation of elliptic curve cryptographic coprocessor over GF(2^m) on FPGA. |
|G. Orlando and C. Paar.
||A high-performance reconfigurable elliptic curve processor for GF(2^m).|
|J. W. Chung, S. G. Sim, and P. J. Lee.
||Fast implementation of elliptic curve defined over GF(p^m) on CalmRISC with MAC2424 coprocessor.|
|10:55 am - 11:15 am||break|
|11:15 am - 12:35 pm
||Power and Timing Analysis Attacks
||Protecting smart cards from passive power analysis with detached power supplies.|
||Smartly analyzing the simplicity and the power of simple power analysis on Smartcards.|
|M. A. Hasan.
||Power analysis attacks and algorithmic approaches to their countermeasures for Koblitz curve cryptosystems.|
||A timing attack against RSA with the Chinese Remainder Theorem.|
|12:35 pm - 2:00 pm||lunch break|
|2:00 pm - 3:20pm
||Hardware Implementation of Block Ciphers
||A. Dandalis, V. K. Prasanna, and J. D. P. Rolim.
||A comparative study of performance of AES final candidates using FPGAs.|
||A dynamic FPGA implementation of the Serpent Block Cipher.|
|S. Trimberger, R. Pang, and A. Singh.
||A 12 Gbps DES Encryptor/Decryptor core in an FPGA.|
|H. Leitold, W. Mayerwieser, U. Payer, K. C. Posch, R. Posch, and J. Wolkerstorfer.
||A 155 Mbps triple-DES network encryptor.|
|3:20 pm - 3:40 pm||break|
|3:40 pm - 5:00pm
||J. Goodman and A. Chandrakasan.
||An energy efficient reconfigurable public-key cryptography processor architecture.|
||High-Speed RSA Hardware based on Barret's Modular Reduction Method.|
||Data integrity in hardware for modular arithmetic.|
|T. Kato, S. Ito, J. Anzai, and N. Matsuzaki.
||A design for modular exponentiation coprocessor in mobile telecommunication terminals.|
|6:00 pm - 9:00 pm
|7:00 pm - 9:00 pm
||Shuttle Service will be provided between WPI, the Crowne Plaza and the Courtyard Marriott|