The aim of the IACR Ph.D. database is twofold. On the first hand, we want to offer an overview of Ph.D. already completed
in the domain of cryptology. Where possible, this should also include a subject classification, an abstract, and
access to the full text.
On the second hand, it deals with Ph.D. subjects
currently under investigation. This way, we provide a timely
map of contemporary research in cryptology.
All entries or changes need to be approved by an editor. You can contact them via phds (at) iacr.org.
Sujoy Sinha Roy (#818)
Sujoy Sinha Roy
Topic of his/her doctorate.
Design and Analysis of Elliptic Curve Cryptosystems on FPGAs
Finite Field Inversion, Itoh Tsujii Inversion, Elliptic Curve Scalar Multiplier, Binary Field, Scheduling, Pipeline, Theoretical Modeling, Efficient Implementation, FPGA
Year of completion
The thesis explores compact and efficient iplementation of elliptic curve cryptography (ECC) on hardware platforms over extended binary fields.
Efficiency of an elliptic curve cryptoprocessor is largely affected by the underlying finite field primitives and by the architecture of the elliptic curve scalar multiplier (ECSM). The work presented in this thesis contributes in designing efficient finite field algorithms by utilizing the Lookup Tables (LUTs) present in FPGAs. The thesis develops a generalization of the Itoh-Tsujii inversion algorithm (ITA) to use higher exponentiation circuits instead of the conventional squaring circuits. Finally the thesis integrates efficient finite field primitives and explores the concept of pipelining to develop a high speed ECSM architecture. The delay of the critical paths of the ECSM architecture have been estimated by a theoretical model and have been split into optimal delay stages. The thesis develops optimal scheduling technique for pipelined ECSM architecture. The work analyzes the effect of increase in number of pipeline stages on the scalar multiplication time and estimates the optimal
number of pipelined stages in the ECSM architecture for a given finite field. Finally detailed analysis, supported with experimental results have been provided to design the fastest reported scalar multiplier in GF(2^163). The proposed design has a three stage pipeline and takes less than 13 us, as compared to 20 us required in the previous best design by Chelton and Benaissa on Virtex 4 FPGAs. Notably, the current design has an area requirement of only 56% compared with the reported work, owing to the better LUT utilizations of the underlying finite field primitives.
sujoyetc (at) gmail.com