IACR News item: 23 February 2016
Souvik Sonar, Debapriya Basu Roy, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay
ePrint Report
Besides security against classical cryptanalysis, its important
for cryptographic implementations to have sucient robustness against
side-channel attacks. Many countermeasures have been proposed to thwart
side channel attacks, especially power trace measurement based side
channel attacks. Additionally, researchers have proposed several evaluation
metrics to evaluate side channel security of crypto-system. However,
evaluation of any crypto-system is done during the testing phase and is
not part of the actual hardware. In our approach, we propose to implement
such evaluation metrics on-chip for run-time side channel vulnerability
estimation of a cryptosystem. The objective is to create a watchdog
on the hardware which will monitor the side channel leakage of the device,
and will alert the user if that leakage crosses a pre-determined threshold,
beyond which the system might be considered vulnerable. Once such
alert signal is activated, proactive countermeasures can be activated either
at the device level or at the protocol level, to prevent the impending
side channel attack. A FPGA based prototype designed by us show low
hardware overhead, and is an eective option that avoids the use of bulky
and inconvenient on-eld measurement setup.
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