IACR News item: 02 January 2016
Sayandeep Saha, Rajat Subhra Chakraborty , Srinivasa Shashank Nuthakki, Anshul, Debdeep Mukhopadhyay
ePrint Report
Test generation for \emph{Hardware Trojan Horses} (HTH) detection is extremely challenging, as
Trojans are designed to be triggered by very rare logic conditions at internal nodes
of the circuit.
In this paper, we propose a \textit{Genetic Algorithm} (GA) based Automatic Test Pattern
Generation (ATPG) technique, enhanced by automated solution to an associated
\textit{Boolean Satisfiability} problem. The main insight is that
given a specific internal trigger condition, it is not possible to attack an arbitrary
node (payload) of the circuit, as the effect of the induced logic malfunction
by the HTH might not get propagated to the output. Based on this observation, a
fault simulation based framework has been proposed, which enumerates the
feasible payload nodes for a specific triggering condition. Subsequently,
a compact set of test vectors is selected based on their ability to detect the logic
malfunction at the feasible payload nodes, thus increasing their effectiveness.
Test vectors generated by the proposed scheme were found to achieve higher
detection coverage over large population
of HTH in ISCAS benchmark circuits,
compared to a previously proposed logic testing based Trojan detection technique.
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