IACR News item: 07 August 2015
Jean-Michel Cioranesco, Roman Korkikian, David Naccache, Rodrigo Portella do Canto
ePrint Report
Fault and power attacks are two common ways of extracting secrets from tamper-resistant chips. Although several protections have been proposed to thwart these attacks, resistant designs usually claim significant area or speed overheads. Furthermore, circuit-level countermeasures are usually not reconfigurable at runtime. This paper exploits the AES\' algorithmic features to propose low-cost and low-latency protections.
We provide Verilog and FPGA implementation details. Using our design, real-life applications can be configured during runtime to meet the user\'s needs and the system\'s constraints.
Additional news items may be found on the IACR news page.