IACR News item: 24 July 2015
Hwajeong Seo, Zhe Liu, Jongseok Choi, Taehwan Park, and Howon Kim
ePrint Reportwas released. This algorithm has certain useful features for hardware
and software implementations, i.e., simple ARX operations, non-S-box
architecture, and 32-bit word size. These features are realized in several
platforms for practical usage with high performance and low overheads.
In this paper, we further improve 128-, 192- and 256-bit LEA encryption
for low-end embedded processors. Firstly we present speed optimization
methods. The methods split a 32-bit word operation into four byte-wise
operations and avoid several rotation operations by taking advantages of
efficient byte-wise rotations. Secondly we reduce the code size to ensure
minimum code size.We nd the minimum inner loops and optimize them
in an instruction set level. After then we construct the whole algorithm
in a partly unrolled fashion with reasonable speed. Finally, we achieved
the fastest LEA implementations, which improves performance by 10.9%
than previous best known results. For size optimization, our implemen-
tation only occupies the 280B to conduct LEA encryption. After scaling,
our implementation achieved the smallest ARX implementations so far,
compared with other state-of-art ARX block ciphers such as SPECK and
SIMON.
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