IACR News item: 28 June 2015
Abhishek Chakraborty, Bodhisatwa Mazumdar, Debdeep Mukhopadhay
ePrint ReportWe considered clock glitch induced faults occurring in practice for a hardware implementation of the cipher to devise our novel attack technique. Our proposed combined attack strategy works well even if the \\emph{useful} ciphertexts are not available to the adversary.
Further, the power trace classifications of a Grain cipher implementation on SASEBO G-II standard side channel evaluation board is shown in order to validate our proposed attack against the cipher.
The captured power traces were analyzed using Least Squares Support Vector Machine (LS-SVM) learning algorithm based multiclass classifiers to classify the power traces into the respective
Hamming distance (HD) classes. To extract power samples with high information about HD classes, Signal-to-noise ratio (SNR) metric
was chosen for feature selection. The experimental results of power trace classifications of test set showed a high success rate of $98\\%$ when the five largest SNR sample instants over a clock cycle were chosen as features. Our proposed attack strategy can also be extended to other stream cipher designs based on Fibonacci
configured shift registers.
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