International Association for Cryptologic Research

International Association
for Cryptologic Research

IACR News item: 24 July 2014

Markku-Juhani O. Saarinen
ePrint Report ePrint Report
Simple AEAD Hardware Interface (S{\\AE}HI) is a hardware cryptographic

interface aimed at CAESAR Authenticated Encryption with Associated

Data (AEAD) algorithms. Cryptographic acceleration is typically

achieved either with a coprocessor or via instruction set

extensions. ISA modifications require re-engineering the CPU core,

making the approach inapplicable outside the realm of open source

processor cores. Our proposed hardware interface is a memory-mapped

cryptographic coprocessor, implementable even on very low end FPGA

evaluation platforms. Algorithms complying to S{\\AE}HI must also

include C language API drivers that directly utilize the

memory mapping in a ``bare metal\'\' fashion. This can also

be accommodated on MMU systems.

Extended battery life and bandwidth resulting from dedicated

cryptographic hardware is vital for currently dominant computing and

communication devices: mobile phones, tablets, and Internet-of-Things

(IoT) applications. We argue that these should be priority hardware

optimization targets for AEAD algorithms with realistic payload

profiles.

We demonstrate a fully integrated implementation of WhirlBob

and Keyak AEADs on the FPGA fabric of Xilinx Zynq 7010. This low-cost

System-on-Chip (SoC) also houses a dual-core Cortex-A9 CPU, closely

matching the architecture of many embedded devices. The on-chip

coprocessor is accessible from user space with a Linux

kernel driver. An integration path exists all the way to end-user

applications.

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