International Association for Cryptologic Research

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2013-09-14
00:17 [Pub][ePrint] Extended Criterion for Absence of Fixed Points, by Oleksandr Kazymyrov and Valentyna Kazymyrova

  One of the criteria for substitutions used in block ciphers is the absence of fixed points. In this paper we show that this criterion must be extended taking into consideration a mixing key function. In practice, we give a description of AES when fixed points are reached. Additionally, it is shown that modulo addition has more advantages then XOR operation.



00:17 [Pub][ePrint] Secure Two-Party Computation with Reusable Bit-Commitments, via a Cut-and-Choose with Forge-and-Lose Technique, by Luís T. A. N. Brandão

  A Secure Two Party Computation (S2PC) protocol allows two parties to compute over their combined private inputs, as if intermediated by a trusted third party. In the active model, security is maintained even if one party is malicious, deviating from the protocol specification. For example, a honest party retains privacy of its input and is ensured a correct output. This can be achieved with a cut-and-choose of garbled circuits (C&C-GCs), where some GCs are verified for correctness and the remaining are evaluated to determine the circuit output.

This paper presents a new C&C-GCs-based S2PC protocol, with significant advantages in efficiency and applicability. First, in contrast with prior protocols that require a majority of evaluated GCs to be correct, the new protocol only requires that at least one evaluated GC is correct. In practice this reduces the total number of GCs to approximately one third, for the same statistical security goal. This is accomplished by augmenting the C&C with a new forge-and-lose technique based on bit commitments with trapdoor. Second, the output of the new protocol includes reusable XOR-homomorphic bit commitments of all circuit input and output bits, thereby enabling efficient linkage of several S2PCs in a reactive manner.

The protocol has additional interesting characteristics (which may allow new comparison tradeoffs). The number of exponentiations is only linear with the number of input and output wires and a statistical parameter -- this is an improvement over protocols whose number of exponentiations is proportional to the number of GCs multiplied by the number of input and output wires. It uses unconditionally hiding bit commitments with trapdoor as the basis of oblivious transfers, with the circuit evaluator choosing a single value and the circuit constructor receiving two (a sort of 2-out-of-1 oblivious transfer, instead of the typical 1-out-of-2). The verification of consistency of circuit input and output keys across different GCs is embedded in the C&C structure.



00:17 [Pub][ePrint] A Method For Generation Of High-Nonlinear S-Boxes Based On Gradient Descent, by Oleksandr Kazymyrov and Valentyna Kazymyrova and Roman Oliynykov

  Criteria based on the analysis of the properties of vectorial Boolean functions for selection of substitutions (S-boxes) for symmetric cryptographic primitives are given. We propose an improved gradient descent method for increasing performance of nonlinear vectorial Boolean functions generation with optimal cryptographic properties. Substitutions are generated by proposed method for the most common 8-bits input and output messages have nonlinearity 104, 8-uniformity and algebraic immunity 3.



00:17 [Pub][ePrint] On Measurable Side-Channel Leaks inside ASIC Design Primitives, by Takeshi Sugawara and Daisuke Suzuki and Minoru Saeki and Mitsuru Shiozaki and Takeshi Fujino

  Leaks inside semi-custom ASIC (Application Specific Integrated Circuit) design primitives are rigorously investigated. The study is conducted by measuring a dedicated TEG (Test Element Group) chip with a small magnetic-field probe on the chip surface. Measurement targets are standard cells and a memory macro cell. Leaks inside the primitives are focused as many of conventional countermeasures place measurability boundaries on these primitives. Firstly, it is shown that current-path leak: a leak based on input-dependent active current path within a standard cell is measurable. Major gate-level countermeasures (RSL, MDPL, and WDDL) become vulnerable if the current-path leak is considered. Secondly, it is shown that internal-gate leak: a leak based on non-linear sub-circuit within a XOR cell is measurable. It can be exploited to bias the distribution of the random mask. Thirdly, it is shown that geometric leak: a leak based on geometric layout of the memory matrix structure is measurable. It is a leak correlated to integer representation of the memory address. We also show that a ROM-based countermeasure (Dual-rail RSL memory) becomes vulnerable with the geometric leak. A general transistor-level design method to counteract the current-path and internal-gate leaks is also shown.





2013-09-12
12:24 [Job][New] PhD scholarship, TU Berlin and DLR and HRS ST, Germany, Europe

  In connection with the „Helmholtz Research School on Security Technologies“ (see www.dlr.de/research_school_security) we are offering an opening for PhD applicants with an outstanding Mathematics/Computer Science/Engineering degree. The successful candidates will have a strong and proven background and as well a self-motivated research interest in at least one of the following research fields:

• sw-induced faultattacks

• fault attacks against crypto systems

• processor bugs in ARM and Intel x86

• excellent programming and Linux system knowledge skills

• computer architecture expertise especially multi-core hw architecture

• reverse engineering of CPU architecture details via patents adn other means

While practically oriented candidates are preferred, outstanding theorists are also considered. Strong candidates are encouraged to send their qualifying applications in electronic form directly to jean-pierre.seifert (at) telekom.de or doerthe.thiel (at) dlr.de

Application materials at www.dlr.de/research_school_security

Technische Universität Berlin and DLR envisage to ensure equal opportunity for men and women, applications from female candidates with the advertised qualifications are explicitly solicited. Provided qualifications are equal, persons with disabilities will be preferred.

09:33 [Job][New] Professors (all ranks), Nazarbayev University, Kazakhstan

  Nazarbayev University is seeking highly-qualified faculty to join its rapidly growing Mathematics program in the School of Science and Technology (SST). Nazarbayev University was launched in 2010 as a premier national and regional university, partnering with some of the most internationally recognized universities in Higher Education.

Applicants should specify their area of expertise as well as its relevance to one of the three groups within the department: pure mathematics, applied mathematics or statistics.

Successful candidates should hold a doctorate degree (Ph.D.), possess strong teaching skills and experience, excellent English-language communication skills and a demonstrated rank-appropriate research accomplishment. International experience is helpful but not required. Positions are available at all ranks (assistant, associate and full professor); visiting faculty positions are also considered.

Position responsibilities include: a teaching load of two courses (on average) per semester, curricular and program development, ongoing engagement in relevant professional and research activities, general program guidance and leadership, student advising, committee service, and other activities related to the intellectual and cultural environment of the university.

Admission to NU is highly competitive. The student body is selected from the top high schools throughout the country and region.

The NU campus is located in Astana, the capital of Kazakhstan, in the heart of the new and ultra-modern Left-Bank region of the city.

Faculty appointments are scheduled to start in July 2014, with the possibility of earlier start dates. Nazarbayev University offers an attractive benefits package, including:

  • competitive compensation;

  • housing based on family size and rank;

  • relocation allowance;

  • air tickets to home country, twice per year;

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09:27 [Event][New] IEEE CCNC 2014 Special Session on Game Theory in Mobile Internet The rapid

  Submission: 13 September 2013
Notification: 4 October 2013
From January 10 to January 13
Location: LAS VEGAS, USA
More Information: http://ccnc2014.ieee-ccnc.org/content/ieee-ccnc




2013-09-11
09:41 [Job][New] Assistant/Associate Professor, Texas Tech University, the Big State, USA

  The Department of Computer Science at Texas Tech University invites applications for a tenure-track position at the rank of assistant or associate professor starting in Fall 2014. Successful candidates must have a Ph.D. in computer science or a closely related field, be able to teach graduate and undergraduate courses, and perform research evidenced by scholarly publications. Successful candidates are also expected to contribute through professional and departmental services. Preference will be given to researchers in cyber security and software engineering, candidates with strong potential to obtain extramural funding. Applications from women and minorities are encouraged.

The Department of Computer Science currently has 14 faculty members with 252 undergraduate and 119 graduate students. Texas Tech University, with an enrollment of 32,000 students, comprises 12 academic colleges/schools and is a part of the state-supported Texas Tech University System. The university shares its campus with the TTU Health Sciences Center.

Lubbock, a city of more than 200,000, is an economic and medical center on the Texas South Plains. The area offers a low cost of living, no state income tax, short commute times, and a rich heritage of music and culture.

Review of applications will begin in September 2013 and continue until the position is filled. A letter of application, curriculum vitae, statement of proposed research, teaching statement, a sample of three papers published, and three letters of reference should be submitted electronically at http://jobs.texastech.edu. Please use Requisition number 86897. The entities of the Texas Tech University System are Equal Opportunity Employers and employ without regard to sex, race, color, national origin, religion, age, disability, genetic information, status as a disabled or Vietnam era veteran, or other protected classes.