International Association for Cryptologic Research

International Association
for Cryptologic Research

IACR News item: 20 September 2012

Nuray At, Jean-Luc Beuchat, Eiji Okamoto, Ismail San, Teppei Yamazaki
ePrint Report ePrint Report
This article describes the design of an 8-bit coprocessor for the AES (encryption, decryption, and key expansion) and the cryptographic hash function Gr{\\o}stl on several Xilinx FPGAs. Our Arithmetic and Logic Unit performs a single instruction that allows for implementing AES encryption, AES decryption, AES key expansion, and Gr{\\o}stl at all levels of security. Thanks to a careful organization of AES and Gr{\\o}stl internal states in the register file, we manage to generate all read and write addresses by means of a modulo-128 counter and a modulo-256 counter. A fully autonomous implementation of Gr{\\o}stl and AES on a Virtex-6 FPGA requires 169 slices and a single 36k memory block, and achieves a competitive throughput. Assuming that the security guarantees of Gr{\\o}stl are at least as good as the ones of the other SHA-3 finalists, our results show that Gr{\\o}stl is the best candidate for low-area cryptographic coprocessors.

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