International Association for Cryptologic Research

International Association
for Cryptologic Research

IACR News item: 06 July 2012

Kris Gaj, Ekawat Homsirikamol, Marcin Rogawski, Rabia Shahid
ePrint Report ePrint Report
In this paper we present a comprehensive comparison of all Round 3 SHA-3 candidates and the current standard SHA-2 from the point of view of hardware performance in modern FPGAs. Each algorithm is implemented using multiple architectures based on the concepts of iteration, folding, unrolling, pipelining, and circuit replication. Trade-offs between speed and area are investigated, and the best architecture from the point of view of the throughput to area ratio is identified. Finally, all algorithms are ranked based on their overall performance in FPGAs. The characteristic features of each algorithm important from the point of view of its implementation in hardware are identified.

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