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Paper: Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results.pdf

Authors:
Julien Francq
Céline Thuillet
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URL: http://eprint.iacr.org/2010/406
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Abstract: Recent cryptanalysis on SHA-1 family has led the NIST to call for a public competition named SHA-3 Contest. Efficient implementations on various platforms are a criterion for ranking performance of all the candidates in this competition. It appears that most of the hardware architectures proposed for SHA-3 candidates are basic. In this paper, we focus on an optimized implementation of the Shabal candidate. We improve the state-of-the-art using the unfolding method. This transformation leads to unroll a part of the Shabal core. More precisely, our design can produce a throughput over 3 Gbps on Virtex-5 FPGAs, with a reasonable area usage.
BibTeX
@misc{eprint-2010-23307,
  title={Unfolding Method for Shabal on Virtex-5 FPGAs: Concrete Results.pdf},
  booktitle={IACR Eprint archive},
  keywords={implementation / hash functions},
  url={http://eprint.iacr.org/2010/406},
  note={ julien.francq@eads.com 14811 received 21 Jul 2010},
  author={Julien Francq and Céline Thuillet},
  year=2010
}