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Paper: Hardware Implementation of the $\eta_T$ Pairing in Characteristic 3

Authors:
Robert Ronan
Colm o hEigeartaigh
Colin Murphy
Tim Kerins
Paulo S. L. M. Barreto
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URL: http://eprint.iacr.org/2006/371
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Abstract: Recently, there have been many proposals for secure and novel cryptographic protocols that are built on bilinear pairings. The $\eta_T$ pairing is one such pairing and is closely related to the Tate pairing. In this paper we consider the efficient hardware implementation of this pairing in characteristic 3. All characteristic 3 operations required to compute the pairing are outlined in detail. An efficient, flexible and reconfigurable processor for the $\eta_T$ pairing in characteristic 3 is presented and discussed. The processor can easily be tailored for a low area implementation, for a high throughput implementation, or for a balance between the two. Results are provided for various configurations of the processor when implemented over the field $\mathbb{F}_{3^{97}}$ on an FPGA. As far as we are aware, the processor returns the first characteristic 3 $\eta_T$ pairing in hardware that includes a final exponentiation to a unique value.
BibTeX
@misc{eprint-2006-21862,
  title={Hardware Implementation of the $\eta_T$ Pairing in Characteristic 3},
  booktitle={IACR Eprint archive},
  keywords={implementation / $\eta_T$ pairing, characteristic 3, elliptic curve, reconfigurable processor, FPGA},
  url={http://eprint.iacr.org/2006/371},
  note={ robertcronan@gmail.com 13448 received 27 Oct 2006},
  author={Robert Ronan and Colm o hEigeartaigh and Colin Murphy and Tim Kerins and Paulo S. L. M. Barreto},
  year=2006
}