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Paper: Application of LFSRs for Parallel Sequence Generation in Cryptologic Algorithms

Authors:
Sourav Mukhopadhyay
Palash Sarkar
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URL: http://eprint.iacr.org/2006/042
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Abstract: We consider the problem of efficiently generating sequences in hardware for use in certain cryptographic algorithms. The conventional method of doing this is to use a counter. We show that sequences generated by linear feedback shift registers (LFSRs) can be tailored to suit the appropriate algorithms. For hardware implementation, this reduces both time and chip area. As a result, we are able to suggest improvements to the design of DES Cracker built by the Electronic Frontier Foundation in 1998; provide an efficient strategy for generating start points in time-memory trade/off attacks; and present an improved parallel hardware implementation of a variant of the counter mode of operation of a block cipher.
BibTeX
@misc{eprint-2006-21535,
  title={Application of LFSRs for Parallel Sequence Generation in Cryptologic Algorithms},
  booktitle={IACR Eprint archive},
  keywords={secret-key cryptography / DES Cracker, TMTO, Counter Mode of Operation, LFSR},
  url={http://eprint.iacr.org/2006/042},
  note={ palash@isical.ac.in 13207 received 6 Feb 2006, last revised 28 Feb 2006},
  author={Sourav Mukhopadhyay and Palash Sarkar},
  year=2006
}