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Paper: VEST Ciphers

Authors:
Sean O'Neil
Benjamin Gittins
Howard A. Landman
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URL: http://eprint.iacr.org/2007/016
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Abstract: VEST (Very Efficient Substitution-Transposition) is a set of families of counter-assisted substitution-transposition ciphers designed and optimised specifically for ASIC and FPGA hardware. VEST ciphers provide fast scalable keystream generation, authenticated encryption and collision-resistant hashing at a very low cost in area and power consumption. All VEST ciphers support variable-length keys and IVs and are naturally very slow in software. Cores of VEST ciphers can be viewed as light-weight T-functions or large bijective nonlinear feedback shift registers (NLFSRs) with massively parallel feedback, assisted by a nonlinear residue number system (RNS) based counter with a very long period. Four VEST cipher family trees are introduced: 80 bit secure VEST4-80, 128 bit secure VEST8-128, 160 bit secure VEST16-160 and 256 bit secure VEST32-256, returning 4 to 32 bits of output per clock cycle while occupying ~3K to ~28K ASIC gates.
BibTeX
@misc{eprint-2007-13298,
  title={VEST Ciphers},
  booktitle={IACR Eprint archive},
  keywords={secret-key cryptography / stream cipher, hash function},
  url={http://eprint.iacr.org/2007/016},
  note={Corrected eSTREAM Phase II submission sean@cryptolib.com 13606 received 21 Jan 2007, last revised 26 Jan 2007, withdrawn 3 Apr 2007},
  author={Sean O'Neil and Benjamin Gittins and Howard A. Landman},
  year=2007
}