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A Presentation on VEST Hardware Performance, Chip Area Measurements, Power Consumption Estimates and Benchmarking in Relation to the AES, SHA-256 and SHA-512

Authors:
Benjamin Gittins
Howard A. Landman
Sean O'Neil
Ron Kelson
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URL: http://eprint.iacr.org/2005/415
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Abstract: A wide-sweeping multi-dimensional analysis and comparison between VEST and the hardware implementations of the AES, AES-HMAC and SHA-2 primitives.
BibTeX
@misc{eprint-2005-12748,
  title={A Presentation on VEST Hardware Performance, Chip Area Measurements, Power Consumption Estimates and Benchmarking in Relation to the AES, SHA-256 and SHA-512},
  booktitle={IACR Eprint archive},
  keywords={implementation / stream ciphers, hash functions, authenticated encryption, message digest, MAC, message authentication code, fastest hardware cipher, NLFSR, parallel feedback, RNS, residue number system, AES, SHA-256, SHA-512, SHA-2, FPGA, ASIC},
  url={http://eprint.iacr.org/2005/415},
  note={posted on ECRYPT, not published previously sean@cryptolib.com 13606 received 17 Nov 2005, last revised 3 Apr 2007, withdrawn 3 Apr 2007},
  author={Benjamin Gittins and Howard A. Landman and Sean O'Neil and Ron Kelson},
  year=2005
}