International Association for Cryptologic Research

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Paper: Partitioned Cache Architecture as a Side-Channel Defence Mechanism

Authors:
D. Page
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URL: http://eprint.iacr.org/2005/280
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Abstract: Recent research has produced a number of viable side-channel attack methods based on the data-dependant behaviour of microprocessor cache memory. Most proposed defence mechanisms are software based and mainly act to increase the attackers workload rather than obviate the attack entirely. In this paper we investigate the use of a configurable cache architecture to provide hardware assisted defence. By exposing the cache to the processor and allowing it to be dynamically configured to match the needs of a given application, we provide opportunity for higher performance as well as security.
BibTeX
@misc{eprint-2005-12614,
  title={Partitioned Cache Architecture as a Side-Channel Defence Mechanism},
  booktitle={IACR Eprint archive},
  keywords={implementation / side-channel attack, cache architecture},
  url={http://eprint.iacr.org/2005/280},
  note={ page@cs.bris.ac.uk 13017 received 22 Aug 2005},
  author={D. Page},
  year=2005
}