International Association for Cryptologic Research

Ph.D. Database

The aim of the IACR Ph.D. database is twofold. On the first hand, we want to offer an overview of Ph.D. already completed in the domain of cryptology. Where possible, this should also include a subject classification, an abstract, and access to the full text. On the second hand, it deals with Ph.D. subjects currently under investigation. This way, we provide a timely map of contemporary research in cryptology. All entries or changes need to be approved by an editor. You can contact them via phds (at)


Kazuo Sakiyama (#460)
Name Kazuo Sakiyama
Personal Homepage
Topic of his/her doctorate. Secure Design Methodology and Implementation for Embedded Public-key Cryptosystems
Category implementation
Keywords public-key cryptography, elliptic curve cryptosystem
Ph.D. Supervisor(s) Bart Preneel, Ingrid Verbauwhede
Year of completion 2007
Abstract Efficient embedded systems are implemented taking into account both hardware and software (HW/SW). In the security domain, cryptosystems need to be resistant against Side-Channel Attacks (SCAs) to protect secret information. Therefore trade-offs between cost, performance and security need to be explored when implementing cryptosystems. The goal for this thesis is to find the best architecture by investigating the trade-offs. The first contribution of this thesis focuses on a HW/SW architecture for Public-Key Cryptography (PKC). We introduce a new scalable and flexible Modular Arithmetic Logic Unit (MALU) that can be used for both RSA and curve-based cryptosystems such as Elliptic Curve Cryptography (ECC) and Hyper-Elliptic Curve Cryptography (HECC). The MALU is the main block in the hardware coprocessor and can accelerate modulo n operations and modular operations over GF(2^m) efficiently. We conclude that the proposed HW/SW platform can be used commonly for developing public-key cryptosystems. The second part of this thesis deals with several case studies that explore the cost and performance trade-offs based on the proposed platform. Two extreme examples of public-key implementations will be introduced; one offers very high performance that is necessary for powerful security systems such as banking servers. By exploiting multi-level parallelism, the proposed ECC processor can perform more than 80 000 point multiplications per second. Another one is targeting a low-power application such as passive RFID tags. We show that the compact version of the MALU consumes less than 30 uW @500 kHz. In addition, we discuss a system-level design flow that can be used for evaluating the security level of hardware implementations against power analysis attacks. The design flow offers an environment to get a quick and correct evaluation of the first order attacks. In this way, we can take the cost for SCA resistance into account in an early stage of the design.
E-Mail Address sakiyama (at)
Last Change 2012-04-26 06:09:14
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Kazuo Sakiyama's Students

Junko Takahashi - Security Evaluation of Side-Channel Resistance for Symmetric Ciphers Using Experimental and Theoretical Approaches (implementation)

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