Publications of ches 2011

Page	Title
1-16	An Exploration of Mechanisms for Dynamic Cryptographic Instruction Set Extension
17-32	FPGA-Based True Random Number Generation Using Circuit Metastability with Adaptive Feedback Control
33-48	Generic Side-Channel Countermeasures for Reconfigurable Devices
49-62	Improved Collision-Correlation Power Analysis on First Order Protected AES
63-78	Higher-Order Glitches Free Implementation of the AES Using Secure Multi-party Computation Protocols
79-94	Protecting AES with Shamir's Secret Sharing Scheme
95-107	A Fast and Provably Secure Higher-Order Masking of AES S-Box
108-123	Software Implementation of Binary Elliptic Curves: Impact of the Carry-Less Multiplier on Scalar Multiplication
124-142	High-Speed High-Security Signatures
143-159	To Infinity and Beyond: Combined Attack on ECC Using Points of Low Order
160-175	Random Sampling for Short Lattice Vectors on Graphics Cards
176-191	Extreme Enumeration on GPU and in Clouds - - How Many Dollars You Need to Break SVP Challenges -
192-206	Modulus Fault Attacks against RSA-CRT Signatures
207-222	Breaking Mifare DESFire MF3ICD40: Power Analysis and Templates in the Real World
223-239	Information Theoretic and Security Analysis of a 65-Nanometer DDSLL AES S-Box
240-255	Thwarting Higher-Order Side Channel Analysis with Additive and Multiplicative Maskings
256-272	Extractors against Side-Channel Attacks: Weak or Strong?
273	Standardization Works for Security Regarding the Electromagnetic Environment
274-291	Meet-in-the-Middle and Impossible Differential Fault Analysis on AES
292-311	On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting
312-325	spongent: A Lightweight Hash Function
326-341	The LED Block Cipher
342-357	Piccolo: An Ultra-Lightweight Blockcipher
358-373	Lightweight and Secure PUF Key Storage Using Limits of Machine Learning
374-389	Recyclable PUFs: Logically Reconfigurable PUFs
390-406	Uniqueness Enhancement of PUF Responses Based on the Locations of Random Outputting RS Latches
407-420	MECCA: A Robust Low-Overhead PUF Using Embedded Memory Array
421-441	FPGA Implementation of Pairings Using Residue Number System and Lazy Reduction
442-458	High Speed Cryptoprocessor for ? T Pairing on 128-bit Secure Supersingular Elliptic Curves over Characteristic Two Fields
459-474	Fast Multi-precision Multiplication for Public-Key Cryptography on Embedded Microprocessors
475-490	Small Public Keys and Fast Verification for $\mathcal{M}$ ultivariate $\mathcal{Q}$ uadratic Public Key Systems
491-506	Throughput vs. Area Trade-offs in High-Speed Architectures of Five Round 3 SHA-3 Candidates Implemented Using Xilinx and Altera FPGAs
507-522	Efficient Hashing Using the AES Instruction Set