Publications of ches 2006

Preface and frontmatter

Page	Title
1-14	Template Attacks in Principal Subspaces
15-29	Templates vs. Stochastic Methods
30-45	Towards Security Limits in Side-Channel Attacks
46-59	HIGHT: A New Block Cipher Suitable for Low-Resource Device
60	Integer Factoring Utilizing PC Cluster
61-75	Optically Enhanced Position-Locked Power Analysis
76-90	Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations
91-100	A Generalized Method of Differential Fault Attack Against AES Cryptosystem
101-118	Breaking Ciphers with COPACOBANA - A Cost-Optimized Parallel Code Breaker
119-133	Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware
134-147	Implementing Cryptographic Pairings on Smartcards
148-159	SPA-Resistant Scalar Multiplication on Hyperelliptic Curve Cryptosystems Combining Divisor Decomposition Technique and Joint Regular Form
160-173	Fast Generation of Prime Numbers on Portable Devices: An Update
174-186	A Proposition for Correlation Power Analysis Enhancement
187-200	High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching
201-215	Cache-Collision Timing Attacks Against AES
216-230	Provably Secure S-Box Implementation Based on Fourier Transform
231	The Outer Limits of RFID Security
232-241	Three-Phase Dual-Rail Pre-charge Logic
242-254	Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage
255-269	Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style
270-284	Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors
285-297	NanoCMOS-Molecular Realization of Rijndael
298-310	Improving SHA-2 Hardware Implementations
311-323	Offline Hardware/Software Authentication for Reconfigurable Platforms
324-338	Why One Should Also Secure RSA Public Key Elements
339-353	Power Attack on Small RSA Public Exponent
354-368	Unified Point Addition Formulæ and Side-Channel Attacks
369-383	Read-Proof Hardware from Protective Coatings
384-398	Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits
399-413	Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks
414	Challenges for Trusted Computing
415-429	Superscalar Coprocessor for High-Speed Curve-Based Cryptography
430-444	Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller
445-459	FPGA Implementation of Point Multiplication on Koblitz Curves Using Kleinian Integers