International Association for Cryptologic Research

Publications by Conference

Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29 - September 1, 2005, Proceedings

Page	Title
1-14	Resistance of Randomized Projective Coordinates Against Power Analysis
15-29	Templates as Master Keys
30-46	A Stochastic Model for Differential Side Channel Cryptanalysis
47-60	A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis
61-74	Further Hidden Markov Model Cryptanalysis
75-90	Energy-Efficient Software Implementation of Long Integer Modular Arithmetic
91-105	Short Memory Scalar Multiplication on Koblitz Curves
106-118	Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP
119-130	SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers
131-146	Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization
147-156	Design of Testable Random Bit Generators
157-171	Successfully Attacking Masked AES Hardware Implementations
172-186	Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints
187-200	Masking at Gate Level in the Presence of Glitches
201-210	Bipartite Modular Multiplication
211-225	Fast Truncated Multiplication for Cryptographic Applications
226-236	Using an RSA Accelerator for Modular Inversion
237-249	Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings
250-264	EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA
265-279	Security Limits for Compromising Emanations
280-292	Security Evaluation Against Electromagnetic Analysis at Design Time
293-308	On Second-Order Differential Power Analysis
309-323	Improved Higher-Order Side-Channel Attacks with FPGA Experiments
324-338	Secure Data Management in Trusted Computing
339-353	Data Remanence in Flash Memory Devices
354-365	Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment
366-382	DPA Leakage Models for CMOS Logic Circuits
383-397	The "Backend Duplication" Method
398-411	Hardware Acceleration of the Tate Pairing in Characteristic Three
412-426	Efficient Hardware for the Tate Pairing Calculation in Characteristic Three
427-440	AES on FPGA from the Fastest to the Smallest
441-455	A Very Compact S-Box for AES