Proceedings of CHES 2005

Resistance of Randomized Projective Coordinates Against Power Analysis., William Dupuy, Sébastien Kunz-Jacques, pp. 1-14

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Templates as Master Keys., Dakshi Agrawal, Josyula R. Rao, Pankaj Rohatgi, Kai Schramm, pp. 15-29

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A Stochastic Model for Differential Side Channel Cryptanalysis., Werner Schindler, Kerstin Lemke, Christof Paar, pp. 30-46

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A New Baby-Step Giant-Step Algorithm and Some Applications to Cryptanalysis., Jean-Sébastien Coron, David Lefranc, Guillaume Poupard, pp. 47-60

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Further Hidden Markov Model Cryptanalysis., P. J. Green, Richard Noad, Nigel P. Smart, pp. 61-74

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Energy-Efficient Software Implementation of Long Integer Modular Arithmetic., Johann Großschädl, Roberto Maria Avanzi, Erkay Savas, Stefan Tillich, pp. 75-90

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Short Memory Scalar Multiplication on Koblitz Curves., Katsuyuki Okeya, Tsuyoshi Takagi, Camille Vuillaume, pp. 91-105

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Hardware/Software Co-design for Hyperelliptic Curve Cryptography (HECC) on the 8051µP., Lejla Batina, David Hwang, Alireza Hodjat, Bart Preneel, Ingrid Verbauwhede, pp. 106-118

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SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers., Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata, Colin Stahlke, pp. 119-130

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Scalable Hardware for Sparse Systems of Linear Equations, with Applications to Integer Factorization., Willi Geiselmann, Adi Shamir, Rainer Steinwandt, Eran Tromer, pp. 131-146

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Design of Testable Random Bit Generators., Marco Bucci, Raimondo Luzzi, pp. 147-156

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Successfully Attacking Masked AES Hardware Implementations., Stefan Mangard, Norbert Pramstaller, Elisabeth Oswald, pp. 157-171

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Masked Dual-Rail Pre-charge Logic: DPA-Resistance Without Routing Constraints., Thomas Popp, Stefan Mangard, pp. 172-186

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Masking at Gate Level in the Presence of Glitches., Wieland Fischer, Berndt M. Gammel, pp. 187-200

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Bipartite Modular Multiplication., Marcelo E. Kaihara, Naofumi Takagi, pp. 201-210

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Fast Truncated Multiplication for Cryptographic Applications., Laszlo Hars, pp. 211-225

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Using an RSA Accelerator for Modular Inversion., Martin Seysen, pp. 226-236

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Comparison of Bit and Word Level Algorithms for Evaluating Unstructured Functions over Finite Rings., Berk Sunar, David Cyganski, pp. 237-249

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EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA., Catherine H. Gebotys, Simon Ho, C. C. Tiu, pp. 250-264

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Security Limits for Compromising Emanations., Markus G. Kuhn, pp. 265-279

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Security Evaluation Against Electromagnetic Analysis at Design Time., Huiyun Li, A. Theodore Markettos, Simon W. Moore, pp. 280-292

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On Second-Order Differential Power Analysis., Marc Joye, Pascal Paillier, Berry Schoenmakers, pp. 293-308

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Improved Higher-Order Side-Channel Attacks with FPGA Experiments., Eric Peeters, François-Xavier Standaert, Nicolas Donckers, Jean-Jacques Quisquater, pp. 309-323

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Secure Data Management in Trusted Computing., Ulrich Kühn, Klaus Kursawe, Stefan Lucks, Ahmad-Reza Sadeghi, Christian Stüble, pp. 324-338

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Data Remanence in Flash Memory Devices., Sergei P. Skorobogatov, pp. 339-353

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Prototype IC with WDDL and Differential Routing - DPA Resistance Assessment., Kris Tiri, David Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede, pp. 354-365

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DPA Leakage Models for CMOS Logic Circuits., Daisuke Suzuki, Minoru Saeki, Tetsuya Ichikawa, pp. 366-382

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The "Backend Duplication" Method., Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, pp. 383-397

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Hardware Acceleration of the Tate Pairing in Characteristic Three., Philipp Grabher, Dan Page, pp. 398-411

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Efficient Hardware for the Tate Pairing Calculation in Characteristic Three., Tim Kerins, William P. Marnane, Emanuel M. Popovici, Paulo S. L. M. Barreto, pp. 412-426

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AES on FPGA from the Fastest to the Smallest., Tim Good, Mohammed Benaissa, pp. 427-440

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A Very Compact S-Box for AES., David Canright, pp. 441-455

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