Much of the information on this web page was provided courtesy of Michael Ley and the DBLP Project

---

CHES 2006:

Yokohama, Japan Louis Goubin and Mitsuru Matsui, (Eds.):
Cryptographic Hardware and Embedded Systems
CHES 2006, 8th International Workshop,
Yokohama, Japan,
October 10-13, 2006,
Proceedings.
Preface, by Louis Goubin and Mitsuru Matsui

Organizing Committee

Tsutomu Matsumoto (General Chair), Yokohama National University, Japan
Çetin Kaya Koç (Publicity Chair), Oregon State University, USA
Louis Goubin (Program Co-chair), Versailles St-Quentin-en-Yvelines University, France
Mitsuru Matsui (Program Co-chair), Mitsubishi Electric Corporation, Japan

Program Committee

Mehdi-Laurent Akkar, Texas Instruments, France
Jean-Sébastien Coron, University of Luxembourg, Luxembourg
Nicolas T. Courtois, Gemalto, France
Joan Daemen, STMicroelectronics, Belgium
Pierre-Alain Fouque, ENS, Paris, France
Jim Goodman, ATI Technologies, Canada
Helena Handschuh, Spansion, France
Tetsuya Izu, Fujitsu Laboratories Ltd, Japan
Marc Joye, Thomson R&D, France
Seungjoo Kim, Sungkyunkwan University, South Korea
Çetin Kaya Koç, Oregon State University, USA
Pil Joong Lee, Postech, South Korea
Frédéric Muller, HSBC, France
Katsuyuki Okeya, Hitachi, Japan
Elisabeth Oswald, Graz University of Technology, Austria
Christof Paar, Ruhr Universität, Bochum, Germany
Josyula R. Rao, IBM T.J. Watson Research Center, USA
Erkay Savaş, Sabanci University, Turkey
Werner Schindler, Bundesamt für Sicherheit in der Informationstechnik, Germany
Nigel Smart, University of Bristol, UK
François-Xavier Standaert, Université Catholique de Louvain-la-Neuve, Belgium
Berk Sunar, Worcester Polytechnic Institute, USA
Frédéric Valette, DGA/CELAR, France
Ingrid Verbauwhede, Katholieke Universiteit Leuven, Belgium
Colin Walter, Comodo CA, UK
Sung-Ming Yen, National Central University, Taiwan

Steering Committee

Marc Joye, Thomson R&D, France
Çetin Kaya Koç, Oregon State University, USA
Christof Paar, Ruhr-Universität Bochum, Germany
Jean-Jacques Quisquater, Université Catholique de Louvain, Belgium
Josyula R. Rao, IBM T.J. Watson Research Center, USA
Berk Sunar, Worcester Polytechnic Institute, USA
Colin D. Walter, Comodo Research Lab, UK

External Referees

---

Side Channels I

• Cédric Archambeau, Eric Peeters, François-Xavier Standaert, Jean-Jacques Quisquater:
  Template Attacks in Principal Subspaces, (.ps). 1-14
  BibTeX
• Benedikt Gierlichs, Kerstin Lemke-Rust, Christof Paar:
  Templates vs. Stochastic Methods, (.ps). 15-29
  BibTeX
• François-Xavier Standaert, Eric Peeters, Cédric Archambeau, Jean-Jacques Quisquater:
  Towards Security Limits in Side-Channel Attacks, (.ps). 30-45
  BibTeX

Low Resources

• Deukjo Hong, Jaechul Sung, Seokhie Hong, Jongin Lim, Sangjin Lee, Bonseok Koo, Changhoon Lee, Donghoon Chang, Jaesang Lee, Kitae Jeong, Hyun Kim, Jongsung Kim, Seongtaek Chee:
  HIGHT: A New Block Cipher Suitable for Low-Resource Device, (.ps). 46-59
  BibTeX

Invited Talk I

• Kazumaro Aoki:
  Integer Factoring Utilizing PC Cluster, (.ps). 60
  BibTeX

Hardware Attacks and Countermeasures I

• Sergei P. Skorobogatov:
  Optically Enhanced Position-Locked Power Analysis, (.ps). 61-75
  BibTeX
• Stefan Mangard, Kai Schramm:
  Pinpointing the Side-Channel Leakage of Masked AES Hardware Implementations, (.ps). 76-90
  BibTeX
• Amir Moradi, Mohammad T. Manzuri Shalmani, Mahmoud Salmasizadeh:
  A Generalized Method of Differential Fault Attack Against AES Cryptosystem, (.ps). 91-100
  BibTeX

Special Purpose Hardware

• Sandeep Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler:
  Breaking Ciphers with COPACOBANA - A Cost-Optimized Parallel Code Breaker, (.ps). 101-118
  BibTeX
• Kris Gaj, Soonhak Kwon, Patrick Baier, Paul Kohlbrenner, Hoang Le, Mohammed Khaleeluddin, Ramakrishna Bachimanchi:
  Implementing the Elliptic Curve Method of Factoring in Reconfigurable Hardware, (.ps). 119-133
  BibTeX

Efficient Algorithms for Embedded Processors

• Michael Scott, Neil Costigan, Wesam Abdulwahab:
  Implementing Cryptographic Pairings on Smartcards, (.ps). 134-147
  BibTeX
• Toru Akishita, Masanobu Katagi, Izuru Kitamura:
  SPA-Resistant Scalar Multiplication on Hyperelliptic Curve Cryptosystems Combining Divisor Decomposition Technique and Joint Regular Form, (.ps) 148-159
  BibTeX
• Marc Joye, Pascal Paillier:
  Fast Generation of Prime Numbers on Portable Devices: An Update, (.ps). 160-173
  BibTeX

Side Channels II

• Thanh-Ha Le, Jessy Clédière, Cécile Canovas, Bruno Robisson, Christine Servière, Jean-Louis Lacoume:
  A Proposition for Correlation Power Analysis Enhancement, (.ps). 174-186
  BibTeX
• Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh:
  High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching, (.ps). 187-200
  BibTeX
• Joseph Bonneau, Ilya Mironov:
  Cache-Collision Timing Attacks Against AES, (.ps). 201-215
  BibTeX
• Emmanuel Prouff, Christophe Giraud, Sébastien Aumônier:
  Provably Secure S-Box Implementation Based on Fourier Transform, (.ps). 216-230
  BibTeX

Invited Talk II

• Ari Juels:
  The Outer Limits of RFID Security, (.ps). 231
  BibTeX

Hardware Attacks and Countermeasures II

• Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti:
  Three-Phase Dual-Rail Pre-charge Logic, (.ps). 232-241
  BibTeX
• Zhimin Chen, Yujie Zhou:
  Dual-Rail Random Switching Logic: A Countermeasure to Reduce Side Channel Leakage, (.ps). 242-254
  BibTeX
• Daisuke Suzuki, Minoru Saeki:
  Security Evaluation of DPA Countermeasures Using Dual-Rail Pre-charge Logic Style, (.ps). 255-269
  BibTeX

Efficient Hardware I

• Stefan Tillich, Johann Großschädl:
  Instruction Set Extensions for Efficient AES Implementation on 32-bit Processors. 270-284
  BibTeX
• Massoud Masoumi, Farshid Raissi, Mahmoud Ahmadian:
  NanoCMOS-Molecular Realization of Rijndael. 285-297
  BibTeX
• Ricardo Chaves, Georgi Kuzmanov, Leonel Sousa, Stamatis Vassiliadis:
  Improving SHA-2 Hardware Implementations, (.ps). 298-310
  BibTeX

Trusted Computing

• Eric Simpson, Patrick Schaumont:
  Offline Hardware/Software Authentication for Reconfigurable Platforms, 311-323
  BibTeX

Side Channels III

• Eric Brier, Benoît Chevallier-Mames, Mathieu Ciet, Christophe Clavier:
  Why One Should Also Secure RSA Public Key Elements, (.ps). 324-338
  BibTeX
• Pierre-Alain Fouque, Sébastien Kunz-Jacques, Gwenaëlle Martinet, Frédéric Muller, Frédéric Valette:
  Power Attack on Small RSA Public Exponent, (.ps). 339-353
  BibTeX
• Douglas Stebila, Nicolas Thériault:
  Unified Point Addition Formulæ and Side-Channel Attacks, (.ps). 354-368
  BibTeX

Hardware Attacks and Countermeasures III

• Pim Tuyls, Geert Jan Schrijen, Boris Skoric, Jan van Geloven, Nynke Verhaegh, Rob Wolters:
  Read-Proof Hardware from Protective Coatings, (.ps). 369-383
  BibTeX
• G. Fraidy Bouesse, Gilles Sicard, Marc Renaudin:
  Path Swapping Method to Improve DPA Resistance of Quasi Delay Insensitive Asynchronous Circuits. 384-398
  BibTeX
• Konrad J. Kulikowski, Alexander B. Smirnov, Alexander Taubin:
  Automated Design of Cryptographic Devices Resistant to Multiple Side-Channel Attacks. 399-413
  BibTeX

Invited Talk III

• Ahmad-Reza Sadeghi:
  Challenges for Trusted Computing, (.ps). 414
  BibTeX

Efficient Hardware II

• Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede:
  Superscalar Coprocessor for High-Speed Curve-Based Cryptography, (.ps). 415-429
  BibTeX
• Manuel Koschuch, Joachim Lechner, Andreas Weitzer, Johann Großschädl, Alexander Szekely, Stefan Tillich, Johannes Wolkerstorfer:
  Hardware/Software Co-design of Elliptic Curve Cryptography on an 8051 Microcontroller, (.ps). 430-444
  BibTeX
• V. S. Dimitrov, Kimmo U. Järvinen, M. J. Jacobson, W. F. Chan, Z. Huang:
  FPGA Implementation of Point Multiplication on Koblitz Curves Using Kleinian Integers, (.ps). 445-459
  BibTeX

---

Author Index

---

Copyright © , IACR